This invention relates to a semiconductor integrated circuit device and to a fabrication process thereof, and more particularly, the invention relates to a technique which is effective when applied to a semiconductor integrated circuit device, which is fabricated by a process including a planarization step using the CMP (Chemical Mechanical Polishing) method.
To satisfy the continuing tendency to decrease the minimum processing size of a semiconductor integrated circuit device, in an exposure optical system, an increase in the performance of a stepper is required, which promotes a widening of the aperture size of a lens and a shortening of the exposure wave length. As a result, the focus depth of the exposure optical system decreases and even a slight unevenness on the surface to be processed becomes a problem. Therefore, the accurate planarization of the surface to be processed becomes an important technical objective for the device process. Furthermore, the above planarization does not aim at the easing of a stepped portion for the purpose of preventing a short cut of interconnections formed on the stepped portion, but is directed to a global planarization, in other words, a complete planarization.
As a surface planarization technique, there are a method of coating an SOG (Spin On Glass) film or a low-melting-point glass by melting it, a method of heat treatment through glass flow, a self planarization method adopting a surface reaction mechanism of CVD (Chemical Vapor Deposition) and the like. Owing to the surface conditions, to the heat treatment conditions being applied or to limitations in processing, in many cases, it is impossible to carry out complete planarization, that is, global planarization, using these methods. Therefore, the etchback and CMP processes are regarded as promising practical techniques which permit complete planarization.
As for the etchback process, the use of a photoresist as a sacrificial film, the use of an SOG film and the use of a self-planarization CVD film are known, but they are accompanied by such drawbacks as a complex procedure, a high cost and a lowering of the yield due to production of particles. The CMP process has, on the other hand, come to be regarded as an excellent process from an overall viewpoint, because, compared with the etchback process, it is more free from the above-described problems. Consequently, the CMP process is considered to be most promising as a practical technique for effecting complete planarization.
The CMP technique is described in, for example, Japanese Patent Application Laid-Open No. HEI 7-74175, U.S. Pat. No. 5,292,689 and xe2x80x9c1996 Symposium on VLSI Technology Digest of Technical Papers, 158-159(1996)xe2x80x9d.
During the investigation of a technique for the complete planarization of a device surface to which the CMP method is applied, which technique is not, however, a known process, the present inventors have recognized that there are the following drawbacks.
FIGS. 29(a) to 29(d) are each a cross-sectional view illustrating a planarization technique using the CMP method which the present inventors have investigated. For covering an interconnection with an insulating film and then planarizing the insulating film, an interconnection 102 is formed on an interlayer insulating film 101 (FIG. 29(a)); a first insulating film 103 and a second insulating film 104, such as SOG, are deposited to embed a concave portion thereof by the plasma CVD method or the like using TEOS (Tetraethoxysilane: (C2H5O)4Si) (FIG. 29(b)); a third insulating film 105 is deposited by the plasma CVD method using TEOS (FIG. 29(c)); and then the third insulating film 105 is polished by the CMP method for effecting planarization (FIG. 29(d)).
At the present time, in the designing of a layout based on principles of functional design and logic design, the most important consideration concerning the pattern of the interconnection 102 has been based on whether the pattern follows the ordinary layout rule or not, and polishing properties in the CMP step have not been taken into particular consideration.
The interconnection pattern is therefore not uniform, being sparse in some places and dense in some places. In the drawing illustrating the technique under investigation (FIG. 29(d)), it is seen that the interconnections 102 are dense in the portion A, while they are sparse in the other region. When CMP polishing is conducted under such a state, that is, a state where interconnections 102 are not disposed uniformly, being sparse in some places and dense in some places, the surface of the third insulating film 105 cannot be planarized completely. In a region where the interconnections 102 are dense, there appears a difference of 0.2 to 0.3 xcexcm in height in the region A and a large undulation inevitably remains on the surface.
On the surface having such an undulation, the processing margin lowers in the subsequent photolithography step or etching step, and it becomes difficult to satisfy minute processing and heightening requirements of integration, which makes it impossible to bring about an improvement in the reliability of the semiconductor integrated circuit device and also an improvement in the yield. In addition, the existence of an undulation requires the optimization of the process conditions in order to carry out lithography and etching favorably in such a state, and an optimization of the CMP step also becomes necessary to suppress the undulation to a minimum. The time required for such optimization sometimes undesirably delays the starting time of the mass-production process.
In the region where the interconnections 102 are disposed sparsely, the recess between the interconnections 102 is not embedded sufficiently with the second insulating film 104, and so the third insulating film 105 must be thicker in order to fill in such a recess completely, which consequently causes problems, such as an increase in the polishing amount of the third insulating film 105 and a rise in the step load in the CMP step, as well as an increase in the step load, such as a long deposition time, of the third insulating film 105.
An object of the present invention is to completely planarize the surface of a member which has been polished by the CMP method.
Another object of the present invention is to provide a technique which can improve the processing margin in the photolithography and etching steps, thereby to achieve minute processing and an increased integration, while, at the same time, improving the reliability and yield of the semiconductor integrated circuit device.
A further object of the present invention is to facilitate the start of the process.
A still further object of the present invention is to reduce the amount of polishing of a member to be polished by the CMP method and to decrease the load and time of the polishing step, thereby improving the cost competitive advantage.
A still further object of the present invention is to provide a method of designing a member pattern which can be planarized completely by the CMP method.
A still further object of the present invention is to suppress an increase in the parasitic capacitance of an interconnection or the like which is caused by the measures to achieve complete planarization, thereby maintaining the performance of the semiconductor integrated circuit device.
The above-described and other objects, and novel features of the present invention will be more apparent from the following description and accompanying drawings.
Typical features of the invention disclosed by the present application will be described briefly.
(1) The semiconductor integrated circuit device according to the present invention comprises actual interconnections which are formed on a principal surface of a semiconductor substrate or an interlayer insulating film constituting a semiconductor integrated circuit element, and an insulating film containing a film which covers the actual interconnections and has been planarized by the CMP method; wherein dummy interconnections, formed of the same material as that of the actual interconnections, but not functioning as an element, are formed in an empty space between adjacent, spaced interconnections in the interconnection layer where said actual interconnections are formed.
In addition, the semiconductor integrated circuit device according to the present invention comprises a shallow trench formed on the principal surface of a semiconductor substrate, an element isolation region having an insulating film, which contains a film planarized by the CMP method, embedded in the shallow trench, and active regions of the semiconductor integrated circuit element separated by said element isolation region, wherein dummy regions, which do not function as a semiconductor integrated circuit element, are formed on the principle surface of the semiconductor substrate in an empty space of the semiconductor substrate between said spaced active regions.
By providing such a semiconductor integrated circuit device with dummy interconnections or dummy regions formed in an empty space to prevent the formation of a sparse portion, the surface of the insulating film which covers the interconnections or the principal surface of the semiconductor substrate can therefore be planarized completely.
Described more specifically, in the case where only actual interconnections or active regions (element constituting members) are formed without dummy interconnections or dummy regions (dummy members), an empty space appears between adjacent but spaced element constituting members. If an insulating film is deposited without eliminating such an empty region, the surface of the insulating film near the empty region becomes uneven reflecting the shape of each of the element constituting members precisely. Such an uneven shape becomes a factor for inhibiting complete planarization, as illustrated in FIG. 29(d).
In accordance with the present invention, therefore, dummy members are disposed in such an empty region to ease the uneven shape of the insulating film, whereby the surface of the insulating film is planarized completely after polishing by the CMP method. The surface of the insulating film is planarized completely in this manner so that the process margin in the subsequent lithography step or etching step can be increased. As a result, the production yield of the semiconductor integrated circuit device can be improved and the starting time for the process can be shortened.
Incidentally, examples of the interconnection include a metal interconnection formed on an interlayer insulating film, a gate interconnection of a MISFET (Metal-Insulator-Semiconductor Field Effect Transistor) and a bit line of a DRAM (Dynamic Random Access Memory). It is needless to say that not only the interconnection of memory devices, such as a DRAM, but also the interconnection of logic devices, are included in the metal interconnection and gate interconnection. In particular, the logic device generally has a multilayer interconnection formed of at least three layers so that the application of the present invention to such an interconnection brings about marked effects.
(2) In another aspect, the semiconductor integrated circuit device according to the present invention contains a high-density member region which satisfies the conditions that the distance between adjacent members of the dummy interconnections and the actual interconnections, or between adjacent members of dummy regions and active regions, is set to at least the minimum space width which is required by the resolution power of lithography, and that said distance is set to at least twice the height of the interconnection or the depth of the shallow trench; and the area of the high-density member region is at least 95% of the whole chip area.
By setting the distance between the adjacent members of the dummy interconnections and the actual interconnections or between the adjacent members of the dummy regions and active regions at not greater than twice the height of the interconnections or depth of the shallow trench, there is no pattern dependence of the member pattern on the CMP polishing rate of the insulating film formed over such members, and the CMP polishing rate becomes uniform, which makes it possible to attain substantially complete surface flatness of the insulating film.
FIG. 30 shows data indicating the finding of the present inventors obtained as a result of test and investigation and it graphically represents the fluctuation of a CMP polishing amount relative to the distance between dummy patterns. The distance between dummy patterns standardized by the height of the pattern is plotted along the abscissa, while the CMP polishing amount of the insulating film on the pattern relative to the standard pattern (solid pattern) is plotted along the ordinate. As is apparent from FIG. 30, the CMP polishing amount of the insulating film does not show a change even it the distance between the dummy patterns becomes approximately twice the height of the pattern. In other words, if the distance between the adjacent members of the dummy interconnections and the actual interconnections, or between the adjacent members of the dummy regions and active regions, is set at not greater than twice the height of the interconnection or the depth of the shallow bench, the CMP rate of the insulating film formed over such members becomes fixed irrespective of the pattern and the insulating film can be planarized completely.
In order to attain planarization over the whole chip, the region where complete planarization can be materialized, that is, the high-density member region preferably is as wide as possible, but it is not necessary for the whole area of the chip to be a high-density member region. A sufficiently flat surface suited for practical use can be obtained so long as the high-density member region permitting complete planarization occupies at least 95% of the chip area.
Another condition that the distance between these members is set at not less than the minimum space width required by the resolution power of lithography is established because a processing space exceeding the minimum processing size is necessary for favorable member processing. It is possible to carry out processing of the interconnections or dummy interconnections, or the active regions or dummy regions, by satisfying the above condition. Incidentally, when a KrF exima laser is used as an exposure source, 0.2 xcexcm can be given as an example of the minimum space width.
Incidentally, in the remaining 5% region which is not a high-density member region, it is preferred that the distance between adjacent members of dummy interconnections and actual interconnections, or between adjacent members of the dummy regions and active regions, is set at not greater than four times the height of the interconnection or the depth of the shallow trench. The polishing amount of the insulating film in such a region where the pattern distance is set at not greater than four times the height of the interconnection or the depth of the shallow trench, that is, a low-density member region shows fluctuations about twice as much as that of the high-density member region, as is illustrated in FIG. 30. Because the area of the low-density member region is not larger than 5% of the chip area, however, the influence of the fluctuation can be neglected.
In addition, in the semiconductor integrated circuit device according to the present invention, the dummy interconnections or dummy regions each have a width not smaller than the minimum line width which is required by the resolution power of lithography, or has a length not smaller than twice the minimum line width; and at the same time, in the scribing area, the width and length of each of the dummy interconnections or dummy regions is not larger than the distance between bonding pads. Incidentally, the minimum space width and minimum line width can each be set at 0.2 xcexcm, and the distance between bonding pads can be set at 10 xcexcm.
According to such a semiconductor integrated circuit device, by setting the width of each of the dummy interconnections or dummy regions at not smaller then the minimum line width, which is required by the resolution power of lithography, the dummy interconnections or dummy regions can be processed with precision; and by setting the length of each of the dummy interconnections or dummy regions at not less than twice the minimum line width, the resolution of such members can be maintained with certainty. In other words, there is a potential problem that a pattern having the minimum processing size in width and length cannot be resolved accurately, but such a potential problem can be avoided in the case of the present invention by setting the length of each of the dummy interconnections or dummy regions at not less than twice the minimum processing size. The width or length of each of the dummy interconnections or dummy regions is set at 30 xcexcm or less, with 20 xcexcm or less being frequently used and with 10 xcexcm or less being preferred.
In addition, by setting each of the width and length of the dummy interconnections or dummy regions at not greater than 30 xcexcm, a parasitic capacitance of the interconnection and the like and also failure due to short circuits between the bonding pads can be reduced. Described specifically, an increase in the width or length of each of the dummy interconnections or dummy regions inevitably enlarges such dummy members, which increases the parasitic capacitance of the interconnection or the like functioning as a semiconductor integrated circuit element and impairs the performance of the semiconductor integrated circuit device, such as the high-speed responsiveness thereof. If the width or length is not greater than 30 xcexcm, on the other hand, it is possible to suppress the parasitic capacitance of the interconnection or the like to an extent not causing a problem in practical use. When the dummy interconnections are disposed in a scribing area, there is a possibility that the scribed chips may become conductive dust. Even if they unfortunately become conductive dust, they cause a short-circuit only between bonding pads. So, by setting the width and length of each of the dummy interconnections at not greater than the distance between the bonding pads, the scribed chips do not cause a short circuit even if they become conductive dust. Owing to these advantages, deterioration in the performance and yield of the semiconductor integrated circuit device can be prevented.
In addition, in the semiconductor integrated circuit device according to the present invention, the dummy interconnections or dummy regions are formed also in the scribing area. According to such a semiconductor integrated circuit device, complete planarization can be maintained even in the scribing area, whereby complete planarization all over the wafer can be actualized.
In addition, in the semiconductor integrated circuit device according to the present invention, a pattern density of interconnections formed of the dummy interconnections and actual interconnections, or a pattern density of regions formed of the dummy regions and active regions, is made substantially uniform all over the regions on the semiconductor substrate.
Even by the semiconductor integrated circuit device as described above, complete planarization of the insulating film on these patterns can be actualized. Described more specifically, as indicated above, the existence of unevenness in the pattern density inhibits the flatness of the insulating film on the pattern. The evenness of the insulating film is therefore improved also by disposing dummy members so as not to cause unevenness in the pattern density.
(3) In a further aspect, the semiconductor integrated circuit device according to the present invention is similar to the above-described one except that, in the same interconnection layer which includes a bonding pad portion or marker portion for photolithography disposed on the semiconductor substrate, dummy interconnections are not formed at the periphery of the bonding pad portion or a marker portion.
Such a semiconductor integrated circuit device makes it possible to smoothly perform automatic detection of a bonding pad upon wire bonding and also automatic detection of a marker used for mask alignment during photolithography. Described more specifically, if dummy members made of the same material as that of the bonding pad or marker have been formed at the periphery thereof, there is a possibility that the dummy members will disturb, in the manner of a noise, the smooth detection of the bonding pad or marker. The present invention is free from such a possibility. Incidentally, it is possible that the dummy interconnections are not formed in a region 20 xcexcm from the bonding pad portion or 60 xcexcm from the marker portion.
In addition, the semiconductor integrated circuit device according to the present invention may contain, as the insulating film, a silicon oxide film formed by the SOG or high-density plasma CVD method, a BPSG (Boron-doped Phospho-Silicate Glass) or PSG (Phospho-Silicate Glass) film formed by the reflow method or a polysilazane film. According to such a semiconductor integrated circuit device, since the silicon oxide film formed by the SOG or high-density plasma CVD method, the BPSG or PSG film formed by the reflow method or the polysilazane film is excellent in step covering properties and has properties of embedding a concave portion therewith, a concave portion formed by adjacent members of the interconnections and dummy interconnections or of the active regions and dummy regions is filled in favorably with such a film, whereby the thickness of the insulating film to be polished by the CMP method can be decreased. Such a decrease in the thickness of the film to be polished by the CMP method leads to not only a reduction in the load of the deposition step of the film to be polished by the CMP method, but also a reduction in the load of the CMP step, which in turn brings about an improvement in the cost competitive advantage of the semiconductor integrated circuit device, for example, by reducing the process time.
The process for the fabrication of a semiconductor integrated circuit device according to the present invention is a process for the fabrication of the above-described semiconductor integrated circuit device, which comprises (a) depositing a conductive film containing polycrystalline silicon or a metal over the principal surface of a semiconductor substrate or over an interlayer insulating film and patterning said conductive film to form actual interconnections and dummy connections, (b) depositing a first insulating film, which is composed of a silicon oxide film formed by the SOG method or high-density plasma CVD method, a BPSG or PSG film formed by the re-flow method or a polysilazane film, over the actual interconnections and dummy interconnections including inner surfaces of concave portions formed by the actual interconnections and dummy interconnections and filling the concave portions with said film, (c) depositing a second insulating film over said first insulating film and (d) polishing the surface of said second insulating film by the CMP method; and wherein the second insulating film is formed to have a thickness sufficient for planarizing the unevenness on the surface of the first insulating film.
According to such a fabrication process of a semiconductor integrated circuit device, the second insulating film can be deposited to give a smaller film thickness, whereby the deposition time of the second insulating film can be shortened; and at the same time, the polishing amount of the second insulating film in the CMP polishing step can be reduced. As a result, in spite of the fact that the above process comprises conventional steps, the step time can be shortened and the step load can be reduced, which brings about an improvement in the cost competitive advantage in a semiconductor integrated circuit device.
Described more specifically, in the fabrication process according to the present invention, the concave portions formed between the actual interconnections and dummy interconnections are filled in with the first insulating film composed of a silicon oxide film formed by the SOG or high-density plasma CVD method, a BPSG or PSG film formed by the re-flow method or a polysilazane film, whereby the unevenness remaining on the surface of the second insulating film is lessened compared with the unevenness before the formation of the film. Accordingly, the thickness of the second insulting film must be sufficient for the planarization of the unevenness on the surface of the first insulating film, but the surface of the second insulating film can be planarized sufficiently even by a thin film.
(4) Incidentally, a rigid pad can be used for said CMP polishing. Alternatively, polishing by the CMP method can be employed only for the surface finish polishing after the unevenness on the surface attributable to the existence of the actual interconnections and dummy interconnections is substantially planarized by the first and second insulating films. As a polishing means employed for the surface finish, not only the CMP method, but also other polishing means, such as dry belt polishing and lapping, may be used.
The process for the fabrication of a semiconductor integrated circuit device according to the present invention is a process for the fabrication of the above-described semiconductor integrated circuit device, which comprises (a) depositing a silicon nitride film on the principal surface of a semiconductor substrate and patterning a portion of the silicon nitride film and semiconductor substrate in regions except for the active regions and dummy regions to form a shallow trench, (b) depositing an insulating film composed of a silicon oxide film on the semiconductor substrate, interconnections and silicon nitride film including the inner surface of the shallow trench, thereby filling in the trench with the insulating film, and (c) polishing the insulating film by the CMP method to expose the silicon nitride film.
According to the above-described fabrication process of a semiconductor integrated circuit device, dummy regions are formed also in an element isolation region so that dishing, that is, the formation of a recess, in the element isolation region can be prevented and the surface of the semiconductor substrate can be planarized completely. In addition, since the silicon nitride film having a lower CMP polishing rate than the silicon oxide film is formed between the insulating film, which is a film to be polished by the CMP method, and the active region of the semiconductor substrate, the silicon nitride film serves as a stopper layer for the CMP polishing and more complete flatness can be attained.
Incidentally, the above process may further comprise a step of using an alkaline slurry, which contains a silicon oxide as an abrasive, as the slurry used for the CMP method in the step (c) and subsequent to the step (c), etching of the insulating film formed in the shallow trench is performed through wet etching or dry etching to make the surface of the insulating film equal to or lower then the principal surface of the semiconductor substrate. When the alkaline slurry containing a silicon oxide as an abrasive is used, the ratio of the polishing rate of the silicon oxide film to the silicon nitride film becomes 3 or 4:1 so that it is necessary to thicken the silicon nitride film. In such a case, when the height of the principal surface of the semiconductor substrate, that is, the active region, and the height of the silicon oxide film, which is an element isolation region after the removal of the silicon nitride film, are compared, the silicon oxide film is found to be higher. The silicon oxide film is therefore etched by wet etching or dry etching to make the surface of the insulating film equal to or lower than the principal surface of the semiconductor substrate, whereby minute gate processing can be carried out.
Alternatively, a slurry containing cerium oxide as an abrasive can be used as the slurry in the CMP method in the step (c). In this case, the ratio of the polishing rate of the silicon oxide film to the silicon nitride film becomes 30 to 50:1 so that it is not necessary to thicken the silicon nitride film. The thickness of the silicon nitride film can be set to a value which is negligible in the process, for example, not greater than 50 nm so that the etching of the silicon oxide film subsequent to the removal of the silicon nitride film is not required.
(5) The method of designing a semiconductor integrated circuit device according to the present invention comprises forming a mask pattern for a mask used for the processing of members each constituting a semiconductor integrated circuit element, wherein said mask pattern includes a member pattern for members and a dummy pattern which is not disposed in a dummy placement prohibited region; and a mask pattern is formed so as to satisfy all of the following conditions: a first condition wherein a pattern distance between adjacent patterns of the member patterns and dummy patterns is not less than the minimum space width which is required by the resolution power of lithography, or not less than 0.2 xcexcm; a second condition wherein the pattern distance is not greater then twice the height of the member in a region of at least 95% of the chip area, and in a region of at most 5% of the chip area, the pattern distance is not greater than four times the height of the member; a third condition wherein the width of the dummy pattern is at least the minimum line width which is required by the resolution power of lithography, or at least 0.2 xcexcm; a fourth condition wherein the width of the dummy pattern is not greater than the distance between bonding pads disposed in the semiconductor integrated circuit device or not greater than 10 xcexcm; a fifth condition wherein the length of the dummy pattern is not less than twice the minimum line width or not less than 0.2 xcexcm; and a sixth condition wherein the length of the dummy pattern is not greater than the distance between the bonding pads or not less than 10 xcexcm.
Such a method of designing a semiconductor integrated circuit device makes it possible to design a mask for member patterns necessary for the fabrication of said semiconductor integrated circuit device. By the above-described conditions, the advantages of the above-described semiconductor integrated circuit device can be actualized.
Incidentally, it is needless to say that the dummy pasterns can be disposed also in a scribing area of the semiconductor substrate. The dummy placement prohibited region can be set within a range of 20 xcexcm from an end portion of the pattern to be a bonding pad, a range of 60 xcexcm from an end portion of the pattern to be a marker for photolithography, a range of 0.5 xcexcm from a region in which a contact hole is to be formed, or a fuse region. By setting the dummy placement prohibited region as described above, it becomes easier to detect the bonding pad or the marker for the mask alignment upon wire bonding or photolithography, which makes it possible to form a contact hole between the interconnections of different layers or a contact hole between the interconnection and the semiconductor substrate.
In the case of a metal interconnection wherein the member and the storage capacitative element which is to be formed above a bit line are formed in substantially the same layer, the dummy placement can be prohibited in a region which is to have a storage capacitative element thereon. In such a case, the first metal interconnection layer and the storage capacitative element of a DRAM can be formed in the same layer and dummy interconnections can be disposed in a region of the first metal interconnection layer.
In the case of the active region wherein members are formed on the principal surface of the semiconductor substrate, the placement of dummy regions can be prohibited in a region wherein a gate interconnection is formed on the principal surface of the semiconductor substrate. In such a case, since no dummy region is formed belong the gate interconnection, the capacitance between the gate interconnection and the semiconductor substrate can be reduced. Described more specifically, because the dummy regions on the principal surface of the semiconductor substrate and the active region of the semiconductor substrate apparently have the same structure, the formation of the gate interconnection on the dummy regions increases the capacitance of the gate interconnection. The dummy regions are therefore not formed below the gate interconnection, which brings about an improvement in the performance of the semiconductor integrated circuit device, such as the high-speed responsiveness thereof.
In addition, the method of designing a semiconductor integrated circuit device according to the present invention comprises disposing dummy patterns so as to minimize the floating capacitance of a member which will otherwise be increased by the dummy members formed by the dummy patterns, whereby the performance of the semiconductor integrated circuit device, such as the high-speed responsiveness thereof, can be improved. Incidentally, such disposal of elements can be effected by satisfying the above-described conditions for the method of designing a semiconductor integrated circuit device and then, optimizing the dummy patterns so as to minimize the area and the number of the dummy patterns. Such optimization can be calculated automatically by an information processor such as computer which forms a layout pattern.